1. Field of the Invention
The present invention generally relates to a method for distributing a clock signal within a semiconductor integrated circuit in a computer-aided design (CAD). More specifically, the present invention is directed to a clock signal distributing method used in a layout of a logic digital integrated circuit by minimizing a clock skew caused by various delays of the digital logic integrated circuit.
2. Description of the Prior Art
Generally speaking, sequential circuits such as flip-flop circuits are employed in a digital logic integrated circuit, and an overall circuit is operated in synchronism with a plurality of clock signals having different phases and periods with respect to each other. Clock signals are produced within an integrated circuit chip, or are supplied thereto from an external device. These clock signals are normally supplied via several staged buffer cells to circuit blocks of this logic digital integrated circuit. In general, buffer cells are automatically connected with each other, and also buffer cells are automatically connected with flip-flops by way of the CAD (computer-aided design) technique.
As is known in the art, there are certain differences in delay time when a clock signal is transferred to each of flip-flop circuits, namely, phase differences among the clock signals. The phase differences are so-called as "clock skew". If the clock skew becomes too great, then the circuit can no longer operate in synchronism with a clock signal having a desirable clock frequency. In other words, the synchronizing operation of this circuit can no longer be maintained at the desirable clock frequency. As a consequence, it is required in an IC chip design to determine positions and wiring paths (route) of buffer cells employed therein in order that clock signals come to all of flip-flops formed on this IC chip at substantially same timings.
There are essentially two typical wiring delays to flip-flops:
internal delays of repeating buffer cells, and PA1 delays occurring when wiring capacitances/resistances of wiring patterns and input terminal capacitances of cells to be driven are charged/discharged by the buffer cells. PA1 grouping said plurality of terminal cells into a plurality of clusters containing at least one of said terminal cells; PA1 forming a binary-tree-shaped wiring pattern path where said root driver cells are constituted as root nodes and said clusters are constituted as leaf nodes; PA1 inserting said repeating buffer cells into portions of the wiring pattern path at which delay time required for transmitting said clock signal in the binary-tree-shaped path is minimized; PA1 calculating first amounts of delays appearing from the respective branch nodes to the leaf nodes, said calculating step being successively repeated from a node positioned at a low level of said binary-tree shaped path to said root nodes; PA1 setting physical positions of said branch nodes on the semiconductor substrate in such a manner that a difference among said calculated first delay amounts becomes minimum; PA1 separating said terminal cells from each other which are overlapped with each other on said binary-tree-shaped path by updating previous entire information about a circuit connection when said repeating buffer cells are inserted, and by correcting arrangement information about positions of the terminal cells adjacent to said buffer cells; PA1 determining a final wiring-pattern path within each of said clusters based upon said corrected arrangement information; PA1 calculating second delay amounts occurring in the clusters based on the finally determined wiring-pattern path; PA1 determining positions of the respective branch nodes based on said second delay amounts; and PA1 determining a final wiring-pattern path among said branch nodes.
With respect to the wire resistances, since sizes of transistors and sectional areas of wiring patterns can be considerably reduced by utilizing the latest semiconductor fine processing techniques, these resistance values are no longer negligible. Accordingly, such a large-scale integration circuit should be handled as a distributed RC network in order to improve prediction of delay times. For instance, a circuit as shown in FIG. 1A should be considered as a distributed RC network as represented in FIG. 1B (will be described in a preferred embodiment).
Then, there are two typical conventional clock-skew reducing methods, for instance, the mesh method and the tree method.
The first-mentioned mesh method has been described in, for instance, Japanese Patent Disclosure No. 63-107316 (1988), in which wiring paths routing chips are formed in a mesh shape, buffer cells are connected adjacent to the wiring paths, and flip-flops are connected to the buffer cells.
This mesh method has the following merits. The structure is simple. Since the wiring path is shaped as a ring form, equivalent resistances of the wiring patterns are lowered, resulting in small delays. Delays can be predicted before the layout process. However, in case of an integration circuit having very large scale, there are problems that clock skew between one flip-flop positioned near a root driver and another flip-flop positioned far from this root driver is no longer negligible, and also since the entire circuit must be segmented by very small meshes, the total wiring length is considerably increased.
On the other hand, in the tree method, buffer cells are connected in parallel with each other at each stage, to constitute a multistage structure, in which tree-shaped wiring paths are formed. The conventional insertion techniques of the buffer cells are described in, for example, Japanese Patent Disclosure No. 61-82455 (1986) and No. 1-157115 (1990). Also, the tree-shaped wiring path techniques are known from, for example, the H-tree shape of H. B. Backoglu, et al.: "A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ulsi and wsi circuits.", IEEE Int. Conf. on Computer Design, 1986.
This conventional tree method has such an advantage that the clock skew can be reduced and this tree method may be readily applied to design semiconductor IC chips having large memory capacities, for instance, so-called "large macro cells" such as ALU and RAM. To the contrary, this tree method has the following drawbacks. When the stage number of buffer cells becomes large, then large delays are caused even though the clock skew may be reduced. Also, it is difficult to predict delays unless a detailed layout process is executed.
As previously explained, although either method has the above-described merits and demerits, the tree method is preferable to designate a large-scaled integrated circuit. Accordingly, a more detailed explanation will be made of the conventional tree method.
The "H-tree" method known as the typical wiring form of the tree method, is such that the H-shaped wiring paths are repeated while being recursively compared and reduced, and equilength or equidistance and equidelay can be maintained in the wiring patterns due to the symmetric shape thereof. However, the above-described delays cannot be achieved unless the total number of elements or element groups is equal to a power of 2, and at the same time, the capacitances of the elements are equal to each other with a symmetrical element arrangement. As a consequence, this H-tree method having such severe conditions may not be practically utilized in the actual circuit design.
To improve this H-tree method, there is the MMM algorithm as described in, Michael A. B. Jackson, et al.: Clock Routing for High-Performance ICs., 27th ACM/IEEE Design Automation Conf., 1990. This conventional method is such that while flip-flops or buffer cells are split in equal number from a top stage to a bottom stage, branch points or junctions of wiring paths are set to gravity positions of the flip-flops positioned within the split regions. Although the process of this tree method is rather simple, the clock skew can be relatively reduced. However, since the tree process is carried out from the top stage to the bottom stage, there is a drawback that a satisfactory skew value may not be obtained, depending upon the precision of delay time prediction.
Furthermore, there is one conventional method to insert buffer cells under optimum condition, i.e., S. Boon, et al.: High performance clock distribution for cmos asic's., IEEE Custom Integrated Circuit Conf., 1989. However, there is a problem that since the wiring method per se has the same algorithm as being used in the normal signal, the large clock skew is caused by differences in the wiring resistances for the respective signal paths when the region to be wired is wide.
As previously stated, in accordance with these conventional methods for distributing the clock signals by the tree methods, although these methods have the same objects, namely reduce the clock skew, the decisions on insertion of the buffer cells and the wiring paths are separately performed with respect to each other. Moreover, as the wiring paths are not determined based upon the detailed delay assumption, very fine balanced clock skew cannot be achieved.